This application claims the benefit of the Korean Application No. P2000-085562 filed on Dec. 29, 2000, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to an array panel, and more particularly, to a thin film transistor array panel pad and a method for fabricating the same that is suitable for use in a digital X-ray detector (DXD).
2. Discussion of the Related Art
Since the X-ray was first discovered in 1895, the medical image field has depended on film as a medium for detecting X-rays. However, film requires development, physical storage, and complicated transmission, all of which take time and money. However, recently developed digital techniques have increasingly replaced film. One of the biggest differences between film and the recently developed digital techniques is the use of digital X-ray devices for obtaining images. The obtained image can be digitized and stored in a computer that provides for subsequent information analysis. Improved image quality, more precise measurements, and improved diagnosis can result form digitized images because various image processing techniques can be used to improve contrast ratios and boundary definitions.
A digital X-ray image apparatus ideally maximizes image sensitivity such that excellent picture quality is obtained using less X-ray radiation than with film. This enables a reduction in the X-ray radiation that is applied to a body. Because an image does not have to be developed on film, the equipment and chemicals necessary or X-ray film development is not required, thereby benefiting the environment. Because a computerized X-ray image can improve obtaining, managing, storing, transmitting, and displaying X-ray images, improved treatments can result.
A digital X-ray detector (DXD) converts an X-ray image into binary data that a computer can recognize. Thus, a digital X-ray image detector is an important part of a digital X-ray system. Generally, a digital X-ray detector includes a thin film transistor (TFT) array panel; an amorphous selenium layer deposited on the TFT array panel; and a transparent electrode formed on the amorphous selenium layer. In operation, X-rays irradiate the amorphous selenium layer, creating electron-hole pairs. The electron-hole pairs are separated and accelerated by a voltage applied across the transparent electrode and another electrode. Electrons are captured at an outer electrode, while holes are captured at an electrode disposed above the TFT. By selectively switching charges captured on the disposed electrodes to electronic networks an X-ray image can be obtained by proper signal processing.
The present invention relates to a DXD TFT array panel, and more particularly to a bonding pad that electrically connects a driving integrated circuit (IC) to a TFT array panel. Generally, the thicker the metal layer of a bonding pad is, the better the contacting force. However, there is a practical limit to the thickness of a bonding pad.
A contact pad of a related art TFT array panel will be explained with reference to the accompanying drawings. FIGS. 1 and 2 are structural sectional views of pads of related art TFT array panels. As shown, a pad of the related art TFT array panel can be comprised of a single metal layer 102a on an insulating substrate 101; or comprised of a first conductive layer 102b and a second conductive layer 103, which is formed by depositing gate or data wire materials on the first conductive layer 102b. 
However, related art TFT array panels have problems. With a single metal layer pad, reference FIG. 1, the thickness of the metal layer 102a must be 4000 xc3x85 (angstroms) or more. However, when depositing metal with such a thickness a significant amount of stress is generated. That stress can result in a hillock being formed, which can lead to electrical shorting. The hillock problem can be reduced by pads having first and second conductive layers 102b and 103, reference FIG. 2. That is, a first metal layer 102b can be deposited and patterned, then a second layer 103 can complete the pad. Even though two layer pads can improve the bonding force with bonding wires, the bonding wire contact area still has a practical limit.
Therefore, a bonding pad having improved bonding force with a wire would be beneficial. Even more beneficial would be a TFT panel having greater contact areas between pads and bonding wires.
Accordingly, the present invention is directed to a thin film transistor (TFT) array panel and to a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is a TFT array panel and a method for fabricating the same that can increase a contact area between a pad and a bonding wire.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a thin film transistor (TFT) array panel defined by an active region and a pad region includes on an insulating substrate a first conductive layer having a plurality of conductive islands and holes. The first conductive layer is in the pad region. A second conductive layer covers the first conductive layer. The second conductive layer extends into the active region and forms a three-dimensionally patterned structure due to the contours of the first conductive layer.
Beneficially, the first conductive layer and the second conductive layer are formed of an aluminum neodymium (AlNd) alloy.
The second conductive layer beneficially extends into an array wire.
Beneficially, the holes and conductive islands form a matrix.
The holes and conductive islands can be circular or tetrahedral. The holes and conductive islands specifically can have rectangular or square cross-sections. The holes and conductive islands can be elongated perpendicular to or parallel with an array wire. The holes and conductive islands beneficially are organized in a matrix. Such matrices can be comprised of holes and/or conductive islands arranged in rows and columns such that all rows and all columns have the same number of holes and/or conductive islands, or different numbers of holes and/or conductive islands. Rows can be spatially offset (with not all rows necessarily having the same number of holes and/or conductive islands), and columns can be spatially offset (with not all columns necessarily having the same number of holes and/or conductive islands).
A method for fabricating the TFT array panel defined by an active region and a pad region includes the steps of: forming a first conductive layer having a plurality of holes and conductive islands in the pad region and on an insulating substrate, and then forming a second conductive layer over the first conductive layer and in the active region such that the first conductive layer is covered.
Accordingly, since the first conductive layer is patterned (beneficially with a constant interval) the second conductive layer has a concave-convex structure, thereby increasing the contact surface area over the related art doubled layer structure.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.